This invention relates to a microprocessor which has an internal cache memory and particularly to the implementation of high speed cache access in the microprocessor.
High levels of chip integration accompanying recent rapid advances in LSI manufacturing technology has made it possible to increase the processing speed of microprocessors by placing on the microprocessor chip high speed instruction execution devices such as pipeline processing formerly used only by mainframe computers.
The operating speed of the external memory, where data the microprocessor needs is stored, already cannot keep up with the speed of the microprocessor. Now that high speed instruction execution devices are being integrated with the microprocessor, the operating speed of the external memory has become a bottleneck.
Microprocessor data access can be accelerated by placing a cache memory, a high speed memory device, between the microprocessor and the former external memory and entering frequently used data from the external memory into the cache memory. Moreover, we can use high integration LSI technology to put the cache memory within the microprocessor itself so that instructions can be entered into the microprocessor even more rapidly.
FIG. 3 is a block diagram of a conventional microprocessor which contains a cache memory. The microprocessor 11 is connected to an external memory 12, which stores data the microprocessor 11 needs. A program counter 13, an address bus 14, an address latch 15 and a cache memory M are also shown in FIG. 3. Multiple addresses are stored in an associative memory unit 16 (hereinafter CAM unit). If an address identical to the address outputted by an address latch 15 is registered, or set, in the CAM unit 16 a match signal corresponding to that address is output on a match line 17. A match signal latch 18 latches the match signal output from the CAM unit 16 on the match line 17. A data memory unit 19 (hereinafter the RAM unit) stores data corresponding to match signals. Data stored in the RAM unit can be accessed through match signals output from a match signal latch 18 on a word line 20. Data which is an output result of a cache memory M is output to a data latch 21. FIG. 3 also shows a data bus 22.
FIG. 4 is a timing chart for the clock signal which determines when the microprocessor 11 performs a reference operation to the cache memory M. Phase A and phase B of FIG. 4 are non-overlapping two phase clock signals.
First, during phase A, the address latch 15 latches the address on the address bus 14 while simultaneously referencing the CAM unit 16 at that address in order to determine if the identical address is registered in the CAM unit 16. If an identical address has been registered, then a corresponding match signal is output on the match line 17. Moreover, during this same phase A, a reference to this same address can be performed on the external memory unit 12.
Next, during phase B, the match signal latch 18 latches the match signal. Concurrently, the match line 17, which is the match line of the match signal latch 18, accesses RAM unit 19 through the word line 20.
During the second phase A, the data latch 21 latches the output results of the cache memory M and decides whether or not the output results are valid.
If the data is valid, the current access to the external memory 12 is canceled and the program counter 13 is incremented to the next reference operation.
If the data is invalid or if the CAM unit 16 does not contain an identical address, the results of the current access to the external memory 12 are needed. Therefore the microprocessor waits until the access to the external memory 12 has been completed before going on to the next reference operation.
The conventional microprocessors such as described above cannot update the contents of the address bus during an instruction fetch before the results of the cache access are output because the cache memory M and the external memory 12 share the address bus 14. Thus the long sequence of events requiring that when the cache memory M is hit, data must first be determined to be valid before the program counter 13 is incremented degrades the efficiency of the access which might begin at the next phase A.